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www.fairchildsemi.com ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 6/27/11 an-9741 design guideline for led lamp control using primary - side regulated flyback converter, FL103M introduction many led lamp systems use the flyback converter topology. in applications where precise output curr ent regulation is required, current sensing in the seco ndary side is always necessary, which results in additional se nsing loss. for power supply designers struggling to meet incre asing regulatory pressures, the output current sensing is a daunting design challenge. primaryside regulation (psr) for power supplies ca n be an optimal solution for compliance and cost in led lamp systems. primaryside regulation controls the outpu t voltage and current precisely with information in the prima ry side of the led lamp controller only. this removes the outp ut current sensing loss and eliminates secondaryfeedb ack circuitry. this facilitates a higher efficiency pow er supply design without incurring tremendous costs. fairchil ds pwm psr controller FL103M simplifies meeting tighte r efficiency requirements with few external component s. this application note presents design consideration s for led lamp systems employing fairchild semiconductor components. it includes designing the transformer a nd output filter, selecting the components, and implem enting constantcurrent control. the stepbystep procedur e completes a power supply design. the design is veri fied through an experimental prototype converter using f l103. figure 1 shows the typical application circuit for an led lamp using FL103M. figure 1. typical application circuit
an9741 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 6/27/11 2 principle of primary-side regulation figure 2 shows typical waveforms of a flyback conve rter. generally, discontinuous conduction mode (dcm) operation is preferred for primaryside regulation since it allows better output regulation. the key of primary side regulation is how to obtain output voltage and curr ent information without directly sensing them. once the se values are obtained, the control can be accomplishe d by the conventional feedback compensation method. i ds i f t on t dis t s v a stage i stage ii stage iii stage i i pk i o = i f_avg s a f n n v s p pk n n i s a o n n v figure 2. key waveforms of psr flyback converter the operation principles of dcm flyback converter a re: stage i during the mosfet on time (t on ), input voltage (v dl ) is applied across the primaryside inductor (l m ). then mosfet current (i ds ) increases linearly from zero to the peak value (i pk ). during this time, the energy is drawn from the input and stored in the inductor. stage ii when the mosfet is turned off, the energy stored in the inductor forces the rectifier diode (d f ) to turn on. during the diode conduction time (t dis ), the output voltage (v o ), together with diode forwardvoltage drop (v f ), are applied across the secondaryside inductor and the diode cu rrent (i f ) decreases linearly from the peak value to zero. at the end of t dis , all the energy stored in the inductor has been de livered to the output. stage iii when the diode current reaches zero, the transforme r auxiliary winding voltage (v a ) begins to oscillate by the resonance between the primaryside inductor (l m ) and the output capacitor of mosfet. design procedure in this section, a design procedure is presented us ing the schematic in figure 3 as a reference. a v o i o v o n i o n f s = 50khz f s = 33khz 0.5*v o n constant voltage operation constant current operation protection o b c uvlo figure 3. cv and cc operation area [step-1] estimate the efficiencies figure 3 shows the constant voltage (cv) and consta nt current (cc) operation area. to optimize the power stage design, the efficiencies and input powers should be specified for operating point a (nominal output vol tage and current), b (50% of nominal output voltage), an d c (minimum output voltage). 1. estimated overall efficiency () for operating poin ts a, b, and c: the overall power conversion efficienc y should be estimated to calculate the input power. i f no reference data is available, set = 0.7 ~ 0.75 for lowvoltage output applications and = 0.8 ~ 0.85 for highvoltage output applications. 2. estimated primaryside efficiency ( p ) and secondaryside efficiency ( s ) for operating points a, b, and c. figure 4 shows the definition of primary side and secondaryside efficiencies, where the primaryside efficiency is for the power transfer f rom ac line input to the transformer primary side, whil e the secondaryside efficiency is for the power tran sfer from the transformer primary side to the power supply output.
an9741 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 6/27/11 3 the typical values for the primaryside and seconda ryside efficiencies are given as: v v o s p 10 ; , 3 2 3 1 < ? ? (1) v v o s p 10 ; , 3 1 3 2 > ? ? (2) figure 4. primary- and secondary-side efficiency with the estimated overall efficiency, the input po wer at nominal output is given as: n o n o in i v p = (3) where v o n and i o n are the nominal output voltage and current, respectively. the input power of the transformer at nominal outpu t is given as: s n o n o t in i v p = _ (4) when the output voltage drops below 50% of its nomi nal value, the frequency is reduced to 33khz to prevent ccm operation. thus, the transformer should be designed for dcm both at 50% of nominal output voltage and minim um output voltage. as output voltage reduces in cc mode, the efficienc y also drops. to optimize the transformer design, it is ne cessary to estimate the efficiencies properly at 50% of nomina l output voltage and minimum output voltage conditions. the overall efficiency at 50% of nominal output vol tage (operating point b) can be approximated as: n o f n o f n o n o b v v v v v v + + ? 5.0 5.0 @ (5) where v f is diode forwardvoltage drop. the secondaryside efficiency at 50% of nominal out put voltage (operating point b) can be approximated as: n o f n o f n o n o s b s v v v v v v + + ? 5.0 5.0 @ (6) then, the power supply input power and transformer input power at 50% nominal output voltage (operating poin t b) are given as: b n o n o b in i v p @ @ 5.0 = (7) b s n o n o b t in i v p @ @ _ 5.0 = (8) the overall efficiency at the minimum output voltag e (operating point c) can be approximated as: n o f n o f o o c v v v v v v + + ? min min @ (9) where, vo min is the minimum output voltage. the secondaryside efficiency at minimum output vol tage (operating point c) can be approximated as: n o f n o f o o s c v v v v v v + + ? min min @ (10) then, the power supply input power and transformer input power at the minimum output voltage (operating poin t c) are given as: c n o o c in i v p @ min @ = (11) c s n o o b t in i v p @ min @ _ = (12) [step-2] determine the dc link capacitor (c dl ) and the dc link voltage range it is typical to select the dc link capacitor as 2 3f per watt of input power for universal input range (90 ~ 265v rms ) and 1f per watt of input power for european input rang e (195 ~ 265v rms ). with the dc link capacitor chosen, the minimum dc link voltage is obtained as: l dl ch in line dl f c d p v v ? ? = ) 1( ) ( 2 2 min min (13) where v line min is the minimum line voltage, c dl is the dc link capacitor, f l is the line frequency, and d ch is the dc link capacitor charging duty ratio defined as sh own in figure 5 (typically about 0.2).
an9741 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 6/27/11 4 2 1 t t d ch = figure 5. dc link voltage waveforms the maximum dc link voltage is given as: max max 2 line dl v v = (14) where v line max is the maximum line voltage. the minimum input dc link voltage at 50% nominal ou tput voltage is given as: l dl ch b in line b dl f c d p v v ? ? = ) 1( ) ( 2 @ 2 min min @ (15) the minimum input dc link voltage at minimum output voltage are given as: l dl ch c in line c dl f c d p v v ? ? = ) 1( ) ( 2 @ 2 min min @ (16) [step-3] determine transformer turns ratio figure 6 shows the mosfet draintosource voltage waveforms. when the mosfet is turned off, the sum o f the input voltage (v dl ) and the output voltage reflected to the primary is imposed across the mosfet as: ro dl nom ds v v v + = max (17) where v ro is reflected output voltage defined as: ( ) f o p s ro v v n n v + = (18) where v f is the diode forward voltage drop and n p and n s are number of turns for the primary side and second ary side, respectively. when the mosfet is turned on; the output voltage, together with input voltage reflected to the second ary, are imposed across the diode as: max dl p s o f v n n v v + = (19) as observed in equations (5) and (6), increasing th e transformer turns ratio (n p /n s ) results in increased voltage of mosfet, while it leads to reduced voltage stress of rectifier diode. therefore, the transformer turns r atio (n p /n s ) should be determined by the compromise between mosfet and diode voltage stresses. when determining the transformer turns ratio, the voltage overshoot (v os ) on drain voltage should be also considered. the maximum volt age stress of mosfet is given as: os ro dl ds v v v v + + = max max (20) for reasonable snubber design, voltage overshoot (v os ) is typically 1~1.5 times the reflected output voltage. it is also typical to have a margin of 15~20% of breakdown vol tage for maximum mosfet voltage stress. s p f o n n v v + ) ( figure 6. voltage stress of mosfet the transformer turns ratio between the auxiliary w inding and secondary winding (n a /n s ) should be determined by considering the permissible ic supply voltage (v dd ) range and minimum output voltage in constant current. whe n the led operates in constant current, v dd is changed, together with the output voltage, as seen figure 7. the over shoot of auxiliary winding voltage caused by the leakage ind uctance also affects the v dd . at lightload condition, where the overshoot of auxiliary winding voltage is negligibl e, v dd voltage is given as: ( ) fa f o s a dd v v v n n v ? + = 1 min (21) the actual v dd voltage at heavy load is higher than equation (21) due to the overshoot by the leakage inductance, which is proportional to the voltage ov ershoot of mosfet draintosource voltage shown in figure 7 . considering the effect of voltage overshoot, the v dd voltages for nominal output voltage and minimum out put voltage are given as: fa os p s f o s a dd v v n n v v n n v ? ? ?? ? ? ?? ? + + ? max (22) fa os p s f o s a dd v v n n v v n n v ? ? ?? ? ? ?? ? + + ? min 2 min (23) where v fa is the diode forwardvoltage drop of auxiliary winding diode.
an9741 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 6/27/11 5 figure 7. v dd and winding voltage [step-4] design the transformer figure 8 shows the definition of mosfet conduction time (t on ), diode conduction time (t dis ), and nonconduction time (t off ). the sum of mosfet conduction time and diode conduction time at 50% of nominal output voltage is obtained as: ? ?? ? ? ?? ? + + = + f o b dl p s b on b dis b on v v v n n t t t 5.0 1 min @ @ @ @ (24) the first step in transformer design is to determin e how much nonconduction time (t off ) is allowed in dcm operation. once the t off is determined, by considering the frequency variation caused by frequency hopping and its own tolerance, the mosfet conduction time is obtained a s: f o b dl p s b off s b on v v v n n t f t + + ? = 5.0 1 1 min @ @ @ (25) t on t dis t s t t off i ds i f figure 8. definition of t on , t dis , and t off transformer primaryside inductance can be calculat ed as: b t in s b on b dl m p f t v l @ _ 2 @ min @ 2 ) ( = (26) the maximum peakdrain current can be obtained at t he nominal output condition as: s m t in pk ds f l p i = _ 2 (27) the mosfet conduction time at the nominal output condition is obtained as: min dl m pk ds on v l i t = (28) the minimum number of turns for the transformer pri mary side to avoid the core saturation is given by: e sat pk ds m p a b i l n = min (29) where a e is the crosssectional area of the core in m 2 and b sat is the saturation flux density in tesla. figure 9 shows the typical characteristics of ferri te core from tdk (pc40). since the saturation flux density (b sat ) decreases as the temperature rises, the hightemper ature characteristics should be considered for a charger in an enclosed case. if there is no reference data, use b sat =0.25~0.3t. once the turns ratio is obtained, determine the pro per integer for n s so that the resulting n p is larger than n p min obtained from equation (29). figure 9. typical b-h curves of ferrite core (tdk/p c40)
an9741 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 6/27/11 6 dcm operation at minimum output voltage should be a lso checked. the mosfet conduction time at minimum outp ut voltage is given as: sr m c t in c dl c on f l p v t = @ _ min @ @ 2 1 (30) where f sr is the reduced switching frequency to prevent ccm operation. then, the nonconduction time at minimum output vol tage is given as: ) 1( 1 min min @ @ @ f o c dl s p c on sr c off v v v n n t f t + + ? = (31) the nonconduction time should be larger than 3s ( 10% of the switching period), considering the tolerance of the switching frequency. [step-5] calculate the voltage and current of the switching devices primary-side mosfet the voltage stress of the mosfet was discussed when determining the turns ratio in step3. assuming tha t drain voltage overshoot is the same as the reflected outp ut voltage, maximum drain voltage is given as: os ro dl ds v v v v + + = max max (32) the rms current though the mosfet is given as: 3 s on pk ds rms ds f t i i = (33) secondary-side diode the maximum reverse voltage and the rms current of the rectifier diode are obtained, respectively, as: max dl p s n o f v n n v v + = (34) s p ro dl rms ds rms f n n v v i i = min (35) [step-6] output voltage and current setting the nominal output current is determined by the sen sing resistor value and transformer turns ratio as: 5.8 = n o s p sense i n n r (36) the voltage divider r 1 and r 2 should be determined such that vs is 2.5v at the end of diode current conduct ion time, as shown in figure 8. 1 2 1 ? = s a ref n o n n v v r r (37) select 1% tolerance resistor for better output regu lation. it is recommended to place a bypass capacitor of 22 ~68pf closely between the vs pin and the gnd pin to bypas s the switching noise and keep the accuracy of the sample d voltage for cv regulation. the value of the capacit or affects the load regulation and constantcurrent regulation . figure 10 illustrates the measured waveform on the vs pin with a different vs capacitor. if a highervalue vs capaci tor is used, the charging time becomes longer and the samp led voltage is higher than the actual value. figure 10. sampling voltage with different vs capac itors fl103 is able to control brownout voltage by vs res istors. when the current through vs (i vs ) is typically 175a, the fl103 triggers brownout protection. at that time, v s is 1.13v. the brownout voltage is obtained, respective ly, as: ? ?? ? ? ?? ? ? = p a dl a n n v v (38) 1 2 r v vs r vs i a vs ? + = (39) when input voltage is low line & output load is hea vy, i vs should be larger than 227a.
an9741 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 6/27/11 7 [step-7] determine the output filter stage the peak to peak ripple of capacitor current is giv en as: pk ds s p co i n n i = (40) the voltage ripple on the output is given by: c co co n o co o dis co o r i i i i c t i v + ? ?? ? ? ?? ? ? = 2 2 (41) sometimes it is impossible to meet the ripple speci fication with a single output capacitor (c o ) due to the high esr (r c ) of the electrolytic capacitor. additional lc filter stages (post filter) can be used. when using post filters, do not to place the corner frequency too low as this may make the system unstable or limit the control bandwidth. it is typical to set the corner frequency of the post filter at a round 1/10 ~ 1/5 of the switching frequency. [step-8] design the rcd snubber in the primary side when the power mosfet is turned off, there is a hig h voltage spike on the drain due to the transformer l eakage inductance. this excessive voltage on the mosfet ma y lead to an avalanche breakdown and, eventually, fai lure of the device. therefore, it is necessary to use an ad ditional network to clamp the voltage. the rcd snubber circu it and mosfet drainvoltage waveform are shown in figure 6 . the rcd snubber network absorbs the current in the leakage inductance by turning on the snubber diode (d sn ) once the mosfet drain voltage exceeds the voltage o f cathode of d sn . in the analysis of snubber network, it is assumed that the snubber capacitor is large enough that its voltage does not change significantly during one sw itching cycle. the snubber capacitor should be ceramic or a material that offers low esr. electrolytic or tanta lum capacitors are unacceptable for these reasons. the snubber capacitor voltage at fullload conditio n (v sn ) is given as: os ro sn v v v + = (42) the power dissipated in the snubber network is obta ined as: s os sn sn pk ds lk sn sn sn f v v v i l r v p ? = = 2 2 ) ( 2 1 (43) where i ds pk is peakdrain current at full load, l lk is the leakage inductance, v sn is the snubber capacitor voltage at full load, and r sn is the snubber resistor. the leakage inductance is measured at the switching frequency on the primary winding with all other win dings shorted. then, the snubber resistor with proper rat ed wattage should be chosen based on the power loss. t he maximum ripple of the snubber capacitor voltage is obtained as: s sn sn sn sn f r c v v = (44) in general, 5~20% ripple of the selected capacitor voltage is reasonable. in the snubber design in this section, neither the lossy discharge of the inductor nor stray capacitance is considered. in the actual converter, the loss in th e snubber network is less than the designed value due to this effect.
an9741 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 6/27/11 8 design example using FL103M table 1. cable compensation application device input output led bulb FL103M 85v ac ~ 265v ac (50hz/60hz) 8.4w (24v/0.36a) description symbol value unit system specifications input minimum line input voltage v line min 85 v ac maximum line input voltage v line max 265 v ac line frequency f l 60 hz setting output voltage v o n 24 v output voltage at point b v o@b 12 v minimum output voltage v o min 10 v normal output current i o n 0.35 a second diode voltage drop v f 1.1 v normal switching frequency f s 50 khz switching frequency between point b and point c f sr 33 khz estimated efficiency input efficiency 0.80 w output secondaryside efficiency s 0.93 input power p in 10.50 input power of transformer p in_t 9.05 overall efficiency at point b @b 0.77 secondaryside efficiency at point b s@b 0.89 input power at point b p in@b 5.48 input power of transformer at point b p in_t@b 4.72 overall efficiency at point c @c 0.75 secondary side efficiency at point c s@c 0.87 input power at point c p in@c 4.64 input power of transformer at point c p in_t@c 4.00 determine dc link capacitor & dc link voltage range input dc link capacitor c dl 20 f output minimum dc link voltage v dl min 86 v maximum dc link voltage v dl max 375 minimum dc link voltage at point b v dl@b min 104 minimum dc link voltage at point c v dl@c min 107 determine the transformer turn ratio input maximum v dd v dd max 24.0 v minimum v dd v dd min 8.0 v dd ripple in burst mode v dd ripple 3.8 v pp v dd diode drop voltage v fa 0.7 v determine n p /n s ratio n p /n s 3.20 determine n a /n s ratio n a /n s 0.68 continued on the following page
an9741 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 6/27/11 9 description symbol value unit output maximum rectifier output voltage v ro 80 v n a /n s ratio 1 n a /n s 1 0.50 n a /n s ratio 2 n a /n s 2 0.24 n a /n s ratio 3 n a /n s 3 0.49 transformer design input nonconduction time at point b t off@b 4.00 us transformer core crosssectional area a e 31.0 mm 2 maximum flux density b sat 0.30 t determine secondary side turns n s 23 turns output mosfet conduction time at point a t on 7.66 us inductor discharge time at point a t dis 8.24 us nonconduction time at point a t off 4.10 us mosfet conduction time at point b t on@b 4.60 us inductor discharge time at point b t dis@b 11.40 us mosfet conduction time at point c t on@c 5.08 us inductor discharge time at point c t dis@c 15.25 us nonconduction time at point c t off@c 9.98 us transformer primaryside inductance l m 1.21 mh peak drain current i ds pk 0.55 a minimum primaryside turns n p min 71.13 turns primaryside turns n p 74 turns auxiliary winding turns n a 16 turns final n p /n s ratio n p /n s 3.22 final n a /n s ratio n a /n s 0.70 selection switching device input mosfet overshoot voltage v os 40 v output mosfet maximum drainsource voltage v ds max 495 v mosfet rms current i ds rms 0.20 a maximum second diode voltage v f 140 v second diode rms current i f rms 0.65 a setting output voltage and current input determine vs highside resistor r1 91 k determine vs lowside resistor r2 16 k determine currentsensing resistor 1 r sense1 2.4 determine currentsensing resistor 2 r sense2 2.2 output calculate vs highside resistor r1 cal 90.85 k auxiliary voltage at low line v a 1 27.52 v auxiliary current at 90v ac i vs low 379.59 ua dc link voltage at brownout v dl bo 38.83 v calculate currentsensing resistor r sense 1.08
an9741 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 6/27/11 10 design summary using FL103M figure 11. schematic for led bulb r201 24k/3216 r101 100k/3216 n l d1 1n4007 d2 1n4007 l101 1mh + c101 10uf/400v + c102 10uf/400v d4 1n4007 output gnd u101 fl103 vdd 3 hv 8 nc 7 gnd 6 nc 4 cs 1 gate 2 vs 5 + c201 100uf/35v c106 2.2n l102 1.5uh r102 120k/3216 c103 4.7n/1kv d101 1n4007 d102 1n4007 d201 egp20d + c104 10uf/50v t101 5 1 2 4 10 9 q101 2n60 r103 10r/2012 r104 100r/2012 r108 2r4/3216 r107 2r2/3216 r105 91k/2012 r106 16k/2012 c105 47pf/2012 d3 1n4007 f1 250v/1a
an9741 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 6/27/11 11 transformer for led bulb core: efd-20 (material: pc-40) bobbin: 10-pin primary 4 3 secondary tape 3t 10 tape 3t tape 3t tape 3t 3 5 2 1 np1 na 9 3mm 3mm ns np2 figure 12. transformer specifications and construct ion table 2. winding specifications no. winding pin (s f) wire turns winding method 1 np1 4 3 0.20 * 1 62 solenoid winding 2 insulation: polyester tape t = 0.05mm, 3 layers 3 ns 10 9 0.32 (tex) * 1 23 solenoid winding 4 insulation: polyester tape t = 0.05mm, 3 layers 5 np2 3 5 0.20 * 1 12 center solenoid winding 6 insulation: polyester tape t = 0.05mm, 3 layers 7 na 2 1 0.20 * 1 16 center solenoid winding 8 outer insulation: polyester tape t = 0.05mm, 3 la yers table 3. electrical characteristics pin specification remark inductance 4 5 1.2mh 7% 1khz, 1v leakage 4 5 maximum 20h short all output pins
an9741 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 6/27/11 12 related datasheets fl103 primary-side regulation pwm controller data sheet disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising ou t of the application or use of any product or circuit descri bed herein; neither does it convey any license unde r its patent rights, nor the rights of others. life support policy fairchilds products are not authorized for use as critical components in life support devices or syst ems without the express written approval of the preside nt of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or s ystems which, (a) are intended for surgical implant into t he body, or (b) support or sustain life, or (c) whose failure t o perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expecte d to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be re asonably expected to cause the failure of the life support d evice or system, or to affect its safety or effectiveness.

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